1. Field of the Invention
This invention relates to a driving technique for a plasma display panel, and more particularly to a method of driving a plasma display panel and an apparatus thereof that is capable of reducing power consumption required for an addressing.
2. Description of the Related Art
Generally, a plasma display panel (PDP) radiates a fluorescent body using an ultraviolet with a wavelength of 147 nm generated upon discharge of an inactive mixture gas, such as He+Xe, Ne+Xe or He+Ne+Xe, to thereby display a picture including characters and graphics. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very improved picture quality owing to a recent technical development. Particularly, since a three-electrode, alternating current (AC) surface-discharge PDP has wall charges accumulated in the surface thereof upon discharge and protects electrodes from a sputtering generated by the discharge, it has advantages of a low-voltage driving and a long life.
In order to express gray levels of a picture, such a PDP is driven by dividing one frame into various sub-fields having a different light-emission frequency. Each sub-field is again divided into a reset period for causing a uniform discharge, an address period for selecting a discharge cell and a sustain period for implementing gray levels depending upon a discharge frequency. For instance, when it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 ms) is divided into 8 sub-fields SF1 to SF8 as shown in FIG. 1. Each of the 8 sub-fields SF1 to SF8 is again divided into a reset period, an address period and a sustain period. Herein, the reset period and the address period of each sub-field are equal every sub-field, whereas the sustain interval and the discharge frequency are increased at a ratio of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field. As mentioned above, since a sustain period is differentiated at each sub-field, gray levels of a picture can be displayed.
The PDP may generate a pseudo contour noise from a moving picture because of a characteristic expressing gray levels of a picture by a combination of sub-fields. If a pseudo contour noise occurs, then a pseudo noise emerges on the field to deteriorate a display quality. For instance, if the field is moved into the left after the left half of the field was displayed at a gray scale value of 128 and the right half of the field was displayed at a gray scale value of 127, then a peak white, that is, a white stripe emerges at a boundary portion between the gray scale values 128 and 127. To the contrary, if the field is moved into the right after the left half of the field was expressed at a gray scale value of 128 and the right half of the field was expressed as a gray scale value of 127, then a black level, that is, a black stripe emerges at a boundary portion between the gray scale values 127 and 128.
In order to eliminate a pseudo contour noise of a moving picture, there has been suggested a scheme of dividing one sub-field to add one or two sub-fields, a scheme of re-arranging a sequence of the sub-fields, a scheme of adding sub-fields and re-arranging a sequence of sub-fields, or an error diffusion method, etc.
Such a PDP driving method is largely classified into a selective writing system and a selective erasing system depending on an emission of the discharge cell selected by the address discharge.
The selective writing system initializes the entire field in the reset period (or set-up period) and thereafter turns on the discharge cells selected by the address discharge. In the sustain period, a discharge of the discharge cells selected by the address discharge is sustained to display a picture.
In the selective writing system, a scanning pulse and a data pulse applied to the scan electrode Y and the address electrode X, respectively has a pulse width set to about 3 μs or more to cause a stable writing discharge within the selected discharge cell.
If the PDP has a resolution of VGA (video graphics array) class, it has total 480 scanning lines. Accordingly, in the selective writing system, an address period within one frame requires total 11.52 ms when one frame interval (i.e., 16.67 ms) includes 8 sub-fields. On the other hand, a sustain period is assigned to 3.05 ms in consideration of a vertical synchronizing signal Vsync. Herein, the address period is calculated by 3 μs(a pulse width of the scanning pulse/the data pulse)×480 lines×8(the number of sub-fields) per frame. The sustain period is a time value (i.e., 16.67 ms−11.52 ms−0.3 ms−1 ms−0.8 ms) obtained by subtracting an address interval of 11.52 ms, once reset interval of 0.3 ms, and an extra time of the vertical synchronizing signal Vsync of 1 ms and an erasure interval of 100 μs×8 sub-fields from one frame interval of 16.67 ms.
In the selective writing system, the sustain period becomes insufficient or fails to be assigned if the sub-fields are added so as to eliminate a pseudo contour noise of a moving picture. For instance, in the selective writing system, if two sub-fields of the 8 sub-fields are divided such that one frame includes 10 sub-fields, then the display period, that is, the sustain period becomes absolutely insufficient. If one frame includes 10 sub-fields, the address period becomes 14.4 ms, which is calculated by 3 μs(a pulse width of the scanning pulse)×480 lines×10(the number of sub-fields) per frame. On the other hand, the sustain period becomes −0.03 ms (i.e., 16.67 ms−14.4 ms−0.3 ms−1 ms−1 ms) which is a time value subtracting an address interval of 14.4 ms, once reset period of 0.3 ms, an erasure interval of 100 μs×10 sub-fields and an extra time of the vertical synchronizing signal Vsync of 1 ms from one frame interval of 16.67 ms.
Accordingly, in such a selective writing system, a sustain period of about 3 ms can be assured when one frame consists of 8 sub-fields, whereas it becomes impossible to assure a time for the sustain period when one frame consists of 10 sub-fields. In order to overcome this problem, there has been suggested a scheme of providing a divisional driving of one field by a double bank system. However, such a scheme raises another problem of a rise of manufacturing cost because it requires an addition of about twice data driving IC's.
A contrast characteristic of the selective writing system is as follows. In the selective writing system, when one frame consists of 8 sub-fields, a light of about 300 cd/m2 corresponding to a brightness of the peak white is produced if a field continues to be turned on in the entire sustain period of 3.05 ms. On the other hand, if the field is sustained in such a state as turned on only in once reset period and turned off in the remaining period within one frame, a light of about 0.7 cd/m2 corresponding to the black is produced. Accordingly, a darkroom contrast ratio in the selective writing system has a level of 430: 1.
The selective erasing system makes a writing discharge of the entire field in the reset period and thereafter turns off the discharge cells selected in the address period by an erasing discharge. Then, in the sustain period, only the discharge cells having not selected by the address discharge are subject to a sustain discharge, thereby displaying a picture.
In the selective erasing system, an erasing data pulse with a pulse width of about 1 μs is applied to the address electrode X so that an erasure discharge can occur within the discharge cells selected during the address discharge. At the same time, a scanning pulse with a pulse width of 1 μs synchronized with the selective erasing data pulse is applied to the scanning electrode Y.
If the PDP having a resolution of VGA (video graphics array) class is driven by a selective erasing system in which one frame interval (i.e., 16.67 ms) is divided into 8 sub-fields, then an address period required within one frame is merely total 3.84 ms. Accordingly, a sustain period can be sufficiently assigned to about 10.73 ms in consideration of a vertical synchronizing signal Vsync. Herein, the address period is calculated by 1 μs(a pulse width of the scanning pulse)×480 lines×8(the number of sub-fields) per frame. The sustain period is a time value (i.e., 16.67 ms−3.84 ms−0.3 ms−1 ms−0.8 ms) obtained by subtracting an address period of 3.84 ms, once reset period of 0.3 ms, and an extra time of the vertical synchronizing signal Vsync of 1 ms and an entire writing time of 100 μs×8(the number of sub-fields) from one frame interval of 16.67 ms. In such a selective erasing system, since the address period is small, the sustain period can be assured even though the number of sub-fields is enlarged. If the number of sub-fields SF1 to SF10 within one frame is enlarged into ten as shown in FIG. 2, then the address period becomes 4.8 ms which is calculated by 1 μs(a pulse width of the scanning/data pulse)×480 lines×10(the number of sub-fields) per frame. On the other hand, the sustain period becomes 9.57 ms which is a time value (i.e., 16.67 ms−4.8 ms−0.3 ms−1 ms−1 ms) obtained by subtracting an address period of 4.8 ms, once reset period of 0.3 ms, an extra time of the vertical synchronizing signal Vsync of 1 ms and the entire writing time of 100 μs×10(the number of sub-fields) from one frame interval of 16.67 ms. Accordingly, the selective erasing system can assure a sustain period at least three times longer than the above-mentioned selective writing system having 8 sub-fields even though the number of sub-fields is enlarged into ten, so that it can realize a bright field with 256 gray levels.
However, the selective erasing system has a disadvantage of low contrast because the entire field is turned on in the entire writing interval as a non-display period. For instance, if the entire field continues to be turned on in the sustain period of 9.57 ms within one frame consisting of 10 sub-fields SF1 to SF10 as shown in FIG. 3, then a light of about 300 cd/M2 corresponding to a brightness of the peak white is produced. A brightness corresponding to the black is 15.7 cd/M2, which is a brightness value of 0.7 cd/M2 generated in once reset period plus a brightness value of 1.5 cd/M2×10(the number of sub-fields) generated in the entire writing interval within one frame. Accordingly, since a darkroom contrast ratio in the selective erasing system is equal to a level of 950:15.7 =60:1 when one frame consists of 10 sub-fields SF1 to SF10, the selective erasing system has a low contrast. As a result, a driving method using the selective erasing system provides a bright field owing to an assurance of sufficient sustain period, but fails to provide a clear field and hence causes a feeling of blurred picture due to a poor contrast.
In order to overcome disadvantages such as a lack of driving time and a deterioration of contrast, etc. occurring in the selective writing system or in the selective erasing system, Korea Patent Application No. 2000-12669, filed by the applicant of this application on Mar. 3, 2000, has suggested a scheme of mapping a data such that the selective write sub-fields co-exists in the selective erasing sub-fields. Such a driving scheme, hereinafter referred to as “SWSE”, provides a data mapping by running parallel with a binary coding and a linear coding like the following Table 1, assuming that one frame should consist of 12 sub-fields corresponding to brightness weighting values of 1, 2, 4, 8, 16, 32, 32, 32, 32, 32, 32 and 32.
TABLE 1GraySF1SF2SF3SF4SF5SF6SF7SF8SF9SF10SF11SF12Level(1)(2)(4)(8)(16)(32)(32)(32)(32)(32)(32)(32) 0~31Binary CodingxxxxxxX32~63Binary Coding0xXXXxX64~95Binary Coding00XXXXX 96~127Binary Coding000XXXX128~159Binary Coding0000XXX160~191Binary Coding00000XX192~223Binary Coding000000X224~255Binary Coding0000000
As can be seen from Table 1, the first to fifth sub-fields SF1 to SF5 arranged at the front of the frame, of the first to twelfth sub-fields SF1 to SF12, is subject to a binary coding while the sixth to twelfth sub-fields (SF6 to SF12) is subject to a linear coding. Each of the seventh to twelfth sub-fields SF7 to SF12 is going to turn off the cells unnecessary for the previous sub-fields.
If a PDP having a resolution of VGA class is driven by a SWSE system as described in Table 1, then an address period and a sustain period within one frame interval are 11.52 ms and 3.35 ms, respectively. Herein, the address period requires 11.52 ms, which is summed 8.64 ms calculated by 3 μs(a pulse width of a selective writing scanning pulse)×480 lines×6 (the number of selective write sub-fields) per frame with 2.88 ms calculated by 1 μs(a pulse width of a selective erasing scanning pulse)×480 lines×6(the number of selective write sub-fields) per frame. The sustain period is 3.35 ms, which is a time value (i.e., 16.67 ms−11.52 ms−0.3 ms−1 ms−0.5 s) obtained by subtracting an address period of 11.52 ms, once reset period of 0.3 ms, an extra time of the vertical synchronizing signal Vsync of 1 ms and an erasing interval of 100 μs×5(the number of sub-fields)=0.5 ms from one frame interval of 16.67 ms. Accordingly, the SWSE system can not only enlarge the number of sub-fields in comparison to the selective writing system to reduce a pseudo contour noise from a moving picture, but also can more enlarge the sustain period from 3.05 ms into 3.35 ms in comparison to the selective writing system.
If a PDP having a resolution of VGA class is driven by a SWSE system as described in Table 1, then a light of about 330 cd/m2 corresponding to a brightness of ‘peak white’ is produced when the entire field is turned on in the display period of 3.35 ms. If the field is turned on only in once reset period within one frame by a reset charge, then a light of 0.7 cd/m2 corresponding to ‘black’ is produced. Accordingly, since a darkroom contrast ratio in the SWSE system is equal to a level of 470:1, a contrast in the SWSE system is more improved than a contrast (i.e., 60: 1) in the selective erasing system that includes 10 sub-fields within one frame and, at the same time, is more increased than a contrast (i.e., 430:1) in the selective writing system that includes 8 sub-fields within one frame.
Meanwhile, the PDP has large power consumption because it has a large size and bulk and is supplied with a high voltage for causing a discharge. A drive integrated circuit (IC) for driving the address electrode X and the scan electrode Y of the PDP causes large power consumption because it must apply a high voltage for causing a discharge to each electrode Y, Z and X. Moreover, power consumption of the drive IC may be increased due to a low efficiency of the PDP.
Most power consumption of the PDP occurs in the sustain period. The address period causes large power consumption next to the sustain period. A power of hundreds of watts is wasted in the sustain period while a power of ens of watts is wasted in the address period. Power consumption in the sustain period is mainly increased or decreased depending on a capacitance value C of of the PDP involves a capacitor C1 between the address electrodes X, a capacitor C2 between the address electrode X and the scan electrode Y, a capacitor C3 between the scan electrode Y and the common sustain electrode Z, and a capacitor C4 between the address electrode X and the common sustain electrode Z. More than 90% of power consumption in the address period is caused by a displacement current generated upon charge/discharge of the PDP. In power consumption in the address period, a magnitude of power onsumption caused by a displacement current can be expressed by the following equation:P=IV=CV2f   (1)wherein C represents a capacitance value between the address electrode X and other electrodes Y and Z being adjacent thereto; V does a voltage of a data pulse; and f does an average switching frequency per unit time of the data drive IC.
As can be seen from the above equation (1), a scheme of reducing power consumption in the address period includes a method of lowering a data voltage V, a method of lowering a capacitance C of the PDP and a method of reducing a switching frequency f of the data drive IC. However, said method of lowering a data voltage V has a limit in reducing such a voltage because the data voltage V is a voltage for allowing the discharge cell to cause a discharge, and has a limit in reducing a capacitance of the PDP because the PDP intends to a high resolution and a large screen. Besides these methods, there is a method of adding an energy recovery circuit for recovering a reactive power from the PDP and then applying the recovered voltage to the PDP using a resonance circuit before an application of a data sustaining voltage. A detailed description as to the energy recovery circuit will be made later.
A condition that the capacitance value C of the PDP is large is when the discharge cells of adjacent sub-pixels have a different logical value as shown in FIG. 5. For instance, such a condition is satisfied at the event of a data pattern in which any one of the discharge cells of adjacent sub-pixels is turned on while other one thereof is turned off. Also, the capacitance value C is large when any one of the discharge cells of adjacent sub-pixels has a low gray scale value while other one thereof has a high gray scale value. A condition that the capacitance value C of the PDP is maximum is a data pattern in which the minimum gray level and the maximum gray level is adjacent to each other in a data pattern in which logical values between the discharge cells of adjacent sub-pixels are different from each other. The data pattern in which the capacitance value C of the PDP becomes maximum is referred to as “sub-pixel switching pattern”.
Since different data voltages, i.e., data voltages of 0V and 70V are applied to adjacent address electrodes X as shown in FIG. 4 in the sub-pixel switching pattern, the capacitance C between the address electrodes X is charged to an extent of a difference of data voltages to have a large leakage current.
A switching frequency f of the data drive IC becomes maximum in the above-mentioned sub-pixel switching pattern. This is caused by a fact that a switching device of the data drive IC repeats its turn-on and turn-off every horizontal period because logical values of vertically adjacent sub-pixels become different. In other words, since a maximum switching frequency f of the data drive IC per one address electrode X in one frame interval is equal to the number of scan lines (i.e., scan electrodes or common sustain electrodes) x the number of sub-fields, a switching device of the data drive IC must repeats its turn-on/off every scanning operation in the sub-pixel switching pattern. For instance, if a resolution is a VGA class and one frame includes 8 sub-fields, then a switching frequency f of the data drive IC is 480(scan line)×8=3840. On the other hand, if one frame includes 12 sub-fields, then a switching frequency f of the data drive IC 480×12=5760.
Also, an average switching frequency of a data pattern that may be generally generated from a moving picture/still picture is large. For instance, in the SWSE driving system, an average switching frequency per electrode line generated at one frame is 3×480 lines +{(0+0+1+2+3+4+5+6)/8}×480 lines=2700. Herein, ‘3×480’ represents a switching frequency per line of the selective write sub-fields SF1 to SF6 obtained by dividing total switching frequency occurring between a gray level range ‘0˜31’ and other gray level range by the number of gray level ranges. Further, ‘{ }’ represents a switching frequency per one line of the selective erase sub-fields SF6 to SF12 obtained by dividing total switching frequency occurring between a gray level range ‘0˜31’ and other gray level range by the number of gray level ranges.
FIG. 6 shows a unit driver circuit of a data drive IC adopting an energy recovery circuit.
Referring to FIG. 6, the unit driver of the data drive IC includes an energy recovery circuit 31 for applying a voltage to the address electrode line X using a voltage recovered from the PDP, and a data driver 32 for switching a voltage applied from the energy recovery circuit depending upon whether or not a data exists.
The energy recovery circuit 31 includes an external capacitor Cs for charging a voltage recovered from the PDP, first and third switches S1 and S3 connected, in parallel, to the external capacitor Cs, an inductor L connected between a node between the first and third switches S1 and S3 and the data driver 32, a second switch S2 connected between an external sustain voltage source Vs and the inductor L, and a fourth switch S4 connected between a ground voltage source GND and the inductor L.
The first switch S1 is turned on before an application of a data, to thereby form a current path between the external capacitor Cs and the address electrode line X of the PDP. The second switch S2 is turned on at a time when the address electrode line X is charged until a sustain voltage level to apply a sustain voltage Vs to the address electrode line X of the PDP. The third switch S3 is turned on just after the PDP generated an address discharge, to thereby form a discharge path between the address electrode line X and the external capacitor Cs. In a time interval when the third switch S3 is turned on, the external capacitor Cs charges a voltage recovered from the PDP. The fourth switch S4 is turned on after a charge of the external capacitor Cs was terminated, to thereby maintain a voltage on the address electrode line X of the PDP at a ground potential GND.
The inductor L and a capacitance Cp of the PDP configures a LC serial resonance circuit, thereby allowing a resonance voltage to be charged into the address electrode line X of the PDP in a time interval when the first switch Si is turned on.
The data driver 32 includes a fifth switch S5 connected to the output terminal of the energy recovery circuit 31, and a sixth switch S6 connected between the fifth switch S5 and the ground voltage source GND. The address electrode line X is connected to an output terminal between the fifth switch S5 and the sixth switch S6.
The fifth switch S5 is turned on in a time interval when a data is inputted under control of a controller, thereby apply a voltage from the energy recovery circuit 31 to the address electrode line of the PDP. Further, the fifth switch S5 is turned off in a time interval when a data does not exist, to thereby cut off a current path between the energy recovery circuit 31 and the PDP.
The sixth switch S6 is turned on in a time interval when a data does not exist under control of the controller, thereby allowing a voltage on the address electrode line X to be kept at a ground voltage, whereas it is turned off in a time interval when a data is inputted.
If the energy recovery circuit is applied to the data drive IC as mentioned above, then power consumption of the data drive IC can be expressed by the following equation:P=IV=CV2f(1−α)  (2)wherein α represents an energy recovery efficiency according to the energy recovery circuit. In the data drive IC, a maximum energy recovery efficiency α is about 0.5.
As described above, in order to reduce a power wasted in the address period, a method of reducing a data voltage or a capacitance of the PDP and an energy recovery circuit may be employed. However, there exists a limit in reducing a data voltage or a capacitance of the PDP, and a limit in reducing power consumption using the energy recovery circuit because an energy recovery efficiency in the addressing operation is low. Therefore, a method of reducing a switching frequency is most effective to reduce a power wasted in the address period.